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Digital Logic Design Model Question Paper | B.Sc. Computer Science Sem 2

Digital Logic Design — Model Question Paper | B.Sc. Computer Science Sem-II

B.Sc. Honours Computer Science Major

Model Question Paper

Semester II

Course 4

Digital Logic Design

Time: 3 Hours Max. Marks: 70

Section – A

Answer any FIVE of the following 5 × 4 = 20 marks
  1. Explain how to represent signed binary numbers.
  2. Distinguish between weighted and non-weighted codes with example.
  3. Draw the logic symbol and write the truth table for:
    a) AND gate
    b) OR gate
  4. What are minterms and maxterms? Give examples for each.
  5. Write about a combinational circuit.
  6. What is a decoder? Give an example.
  7. Write short notes on priority encoder.
  8. Differentiate between a latch and a flip-flop.

Section – B

Answer any FIVE of the following 5 × 10 = 50 marks

UNIT — I

9. (a)Convert the following:
  • i) (53.625)10 to ( ? )2
  • ii) (4095)10 to ( ? )16
  • iii) (2D7)16 to ( ? )8
  • iv) (777)8 to ( ? )2
OR
9. (b)Find the 1’s and 2’s complements of the following 8-digit binary numbers:
  • i) 10101110
  • ii) 10000001
  • iii) 10000000
  • iv) 00000001
  • v) 00000000

UNIT — II

10. (a)Simplify the following Boolean functions using a three-variable K-map:
  • a) F(x, y, z) = Σ(0, 1, 5, 7)
  • b) F(x, y, z) = Σ(0, 1, 2, 3, 6, 7)
OR
10. (b)Describe the postulates and theorems of Boolean algebra.

UNIT — III

11. (a)Define half-adder. Design a half-adder using logic gates.
OR
11. (b)What is a full-adder? Implement a full-adder using two half-adders and one OR gate.

UNIT — IV

12. (a)What is a multiplexer? Implement the Boolean function F(A, B, C) = Σ(1, 3, 5, 6) with a multiplexer.
OR
12. (b)Draw the logic diagram of a 2:4 decoder with an ENABLE input using:
  • i) NAND gates
  • ii) NOR gates

UNIT — V

13. (a)Explain the operation of an RS flip-flop with a logic diagram.
OR
13. (b)Explain the operation of a JK flip-flop with a logic diagram.

Digital Logic Design — Model Question Paper · B.Sc. Computer Science, Semester II

Updated: September 27, 2026 — 2:44 pm
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